The present invention relates to a frequency multiplier using a voltage-controlled delay circuit and, in particular, to a frequency multiplier for use in a microcomputer and DSP (digital signal processor).
FIG. 9 shows a conventional ordinary N-multiplying frequency multiplier. A reference signal Fref is supplied to an input terminal of a voltage-controlled delay circuit (VCD)1 and also to a first input terminal of a phase comparator (PHC) 3. An output signal Fdel of the voltage controll ed delay circuit 1 is supplied to an inverter 2. An output signal Fdeln of the inverter 2 is supplied to a second input terminal of the phase comparator 3. The phase comparator 3 detects a phase difference between the falls or rises of both signals Fref and Fdeln and an error signal Verr corresponding to the phase difference is supplied to an input terminal of a lowpass filter (LPF) 4. The lowpass filter 4 takes out only a DC component of the error signal Verr and supplies it as a control voltage Vcont to a voltage controlled delay circuit 1. If feedback control is effected to cancel the phase difference between the reference signal Fref and the delay signal Fdeln, then the output signal Fdel of the voltage controlled delay circuit 1 becomes a half-period delayed reference signal Fref.
The voltage controlled delay circuit 1 is comprised of a plurality of series-connected inverter circuits. The reference signal Fref is supplied to an input terminal of an initial stage inverter circuit and an output terminal of a final stage inverter circuit produces a delayed replica Fdel of the reference signal Fref. The voltage controlled delay circuit 1 has an n number of intermediate terminals. With k representing a natural number 1 to N, the k-th intermediate terminal produces a delay signal Fk obtained by delaying the reference signal Fref by (k-1)/N times the whole delay time of the delay signal Fdel to the reference signal Fref. That is, the delay signal F1 is the same as the reference signal Fref, the delay signal F2 is delayed behind the reference signal Fref by 1/N times the whole delay time, and the delay signal FN is delayed behind the reference signal Fref by (N-1)/N times the whole delay time.
The N-multiplying logic circuit 24 is comprised of an N/2 number of exclusive OR gates 5-1 to 5-N/2 and an adder 8. Delay signals F1 and F2 output from the voltage controlled delay circuit 1 are supplied to first and second input terminals of the exclusive OR gate 5-1. An output signal D1 of the exclusive OR gate 5-1 is supplied to a first input terminal of the adder 8. In this way, delay signals F(N-1) and FN output from the voltage controlled delay circuit 1 are supplied to first and second input terminals of the exclusive OR gate 5-N/2 and an output signal N/2 of the exclusive OR gate 5-N/2 is supplied to an N/2-th input terminal of the adder 8. The output signal of the adder 8 becomes an N-multipled signal Fout of the reference signal Fref.
The circuit above produces the N-multiplied signal with the use of both the rise and fall of the delay signal (F1 to FN).
Since, generally, the operation speed of an NMOS transistor constituting an inverter is faster than the operation speed of a PMOS transistor, the rise and fall times of the signal propagating over the inverters of the voltage controlled delay circuit 1 vary.
As a result, the signal propagating in the voltage controlled delay circuit 1 becomes sometimes shorter in the high period than in the low period. An N multiplying signal, being composed from a signal whose duty ratio is not 50%, produces frequency jitters.
Under these situation, in order to make the operation speed of the NMOS transistor and that of the PMOS transistor equal to each other, control has sometimes been made on the transistor sizes, such as the channel length or channel width, of the PMOS and NMOS transistors. It has been very difficult, however, to obtain exactly the same speed between both the type of transistors because there is a variation in the manufacturing condition and in the threshold voltage Vth of these transistors.
Further, it has not been possible for the conventional circuit to, upon receipt of a reference signal whose duty ratio is not 50%, compose a multiplied signal by itself.
As set out above, there has been restriction to the reference signal in the conventional technique. Further, the duty ratio of the multiplied signal does not become 50% and the multiplied signal involves frequency jitters. It has been difficult to obtain an accurate multiplied signal.